1. Field of the Invention
The present invention relates to an analysis method used in a static timing analysis (STA) tool, and more particularly, to a timing analysis method for a semiconductor circuit or logic circuit having a low-voltage swing bus.
2. Description of the Related Art
Semiconductor memory devices such as dynamic random access memories (DRAMs) or application-specific integrated circuits (ASIC) are released into the market after a design process, manufacturing, and semiconductor chip testing or a test for semiconductor packages. During the design process, static timing analysis (hereinafter, STA) is performed by analyzing the timings of signals input to or output from the designed circuit, to ensure that the designed circuit works properly. An STA tool performs STA when it receives the designed circuit. During STA, delay models for cells included in the designed circuit are extracted from a database. The database stores delay models for cells, including transistor level cells, gate level cells, unit logic (AND, OR, and the like) level cells, or other cells, such as a sense amplifying flip-flop, in which it is difficult to calculate delays. Next, the timings for input and/or output signals of each cell are analyzed. After that, delays between nodes of the designed circuit are reported to a user. U.S. Pat. No. 4,924,430 discloses such an STA.
During a high-performance design process, a low voltage swing bus is generally used to interface with the semiconductor or logic circuit. The semiconductor or logic unit benefits from the speed and power consumption of the low voltage swing bus.
The low voltage swing bus is a signal interface line, which is designed not to experience a full supply voltage VDD swing in the semiconductor circuit or logic circuit, but rather experience the full supply voltage VDD swing in response to a voltage that is less than the supply voltage VDD after a receiving end senses a signal fed from a transmitting end.
FIG. 1 is a block diagram illustrating a low voltage swing bus according to conventional art, and FIG. 2 illustrates a waveform for describing the timing of input or output signals in the low voltage swing bus of FIG. 1.
Referring to FIG. 1, two signal lines operate as a pair and transmit the logic signals LSH and LSL, which are inverted with respect to each other (hereinafter, a signal line LSH and a signal line LSL).
Referring to FIG. 2, signals are transmitted or received through the low voltage swing bus in the following manner. First, the signal lines LSH and LSL are precharged to the supply voltage VDD. Next, one of the two signal lines LSH and LSL enters a logic state opposite to that of the precharging voltage. In other words, referring to FIGS. 1 and 2, when an input signal INH is high and an input signal INL is low, only the signal line LSH enters a logic low state and the signal line LSL maintains a logic high level. At that moment, the signal line LSH does not experience the full supply voltage VDD swing. When the voltage difference between the signal line LSH and the signal line LSL reaches Vs, a sense amplifying flip-flop, senses and amplifies the voltage difference Vs and outputs an active signal QH and an inverted signal QL of the active signal QH.
In such a low voltage swing bus, the delay between the signal to be transmitted to and the signal output from a sense amplifying flip flop (hereinafter, a sense amplifying flip flop) relates to the time necessary for the signal line LSH to reach the minimum voltage difference Vs that can be sensed by the sense amplifying flip flop, i.e., corresponds to Treal of FIG. 2. However, during timing analysis of the low voltage swing bus, when using the STA tool, the delay between the signal transmitted to and the signal output from the sense amplifying flip flop is equal to the delay between signals that experience 50% of the full supply voltage VDD swing, according to a general delay model for the sense amplifying flip flop. As a result, incorrect delays are reported to the user.
In order to solve such a problem, delays between nodes, which are included in the low voltage swing bus, and the sense amplifying flip flop are obtained as a result of SPICE (Simulation Program with Integrated Circuit Emphasis, hereinafter SPICE), and stored in the database of the STA tool. Hence, the STA tool can refer to the results of SPICE simulation using a command file. However, timing analysis that includes modelling of the low voltage swing bus and sense amplifying flip flop, execution of SPICE simulation, and application of the STA tool is complex, inconvenient, and causes considerable loss of time.